Computer Architecture - Syllabus

Embark on a profound academic exploration as you delve into the Computer Architecture course (CA) within the distinguished Tribhuvan university's CSIT department. Aligned with the 2074 Syllabus, this course (CSC208) seamlessly merges theoretical frameworks with practical sessions, ensuring a comprehensive understanding of the subject. Rigorous assessment based on a 60 + 20 + 20 marks system, coupled with a challenging passing threshold of , propels students to strive for excellence, fostering a deeper grasp of the course content.

This 3 credit-hour journey unfolds as a holistic learning experience, bridging theory and application. Beyond theoretical comprehension, students actively engage in practical sessions, acquiring valuable skills for real-world scenarios. Immerse yourself in this well-structured course, where each element, from the course description to interactive sessions, is meticulously crafted to shape a well-rounded and insightful academic experience.

Course Description: This course includes concepts of instruction set architecture,

organization or micro-architecture, and system architecture. The instruction set architecture

includes programmer’s abstraction of computer. The micro-architecture consist internal

representation of computers at register and functional unit level. The system architecture

includes organization of computers at the cache and bus level.

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Course Objectives

•  Discuss representation of data and algorithms used to perform operations on data
•  Demonstrate different operations in terms of Micro-operations
•  Explain architecture of basic computer and micro-programmed control unit
•  Understand and memory and I/O organization of a typical computer system
•  Demonstrate benefits of pipelined systems

Data Representation

1.1. Data Representation: Binary Representation, BCD, Alphanumeric Representation,

Complements, Fixed Point representation, Representing Negative Numbers, Floating

Point Representation, Arithmetic with Complements, Overflow, Detecting Overflow

1.2. Other Binary Codes: Gray Code, self Complementing Code, Weighted Code, Excess-3

Code, EBCDIC

1.3. Error Detection Codes: Parity Bit, Odd Parity, Even parity, Parity Generator & Checker

Register Transfer and Microoperations

2.1. Microoperation, Register Transfer Language, Register Transfer, Control Function

2.2. Arithmetic Microoperations: Binary Adder, Binary Adder-subtractor, Binary

Incrementer, Arithmetic Circuit

2.3. Logic Microoperations, Hardware Implementation, Applications of Logic

Microoperations.

2.4. Shift Microoperations: Logical Shift, Circular shift, Arithmetic Shift, Hardware

Implementation of Shifter.

Basic Computer Organization and Design

3.1. Instruction Code, Operation Code, Stored Program Concept

3.2. Registers and memory of Basic Computer, Common Bus System for Basic Computer.

3.3. Instruction Format, Instruction Set Completeness, Control Unit of Basic Computer, Control Timing Signals

Microprogrammed Control

4.1. Control Word, Microprogram, Control Memory, Control Address Register,

Sequencer

4.2. Address Sequencing, Conditional Branch, Mapping of Instructions, Subroutines,

Microinstruction Format, Symbolic Microinstructions

4.3. Design of Control Unit

Central Processing Unit

5.1. Major Components of CPU, CPU Organization

5.2. Instruction Formats, Addressing Modes, Data Transfer and manipulation, Program Control, Subroutine Call and Return, Types of Interrupt

5.3. RISC vs CISC, Pros and Cons of RISC and CISC, Overlapped Register Windows

Pipelining

6.1. Parallel Processing, Multiple Functional Units, Flynn’s Classification

6.2. Pipelining: Concept and Demonstration with Example, Speedup Equation, Floating

Point addition and Subtraction with Pipelining

6.3. Instruction Level Pipelining: Instruction Cycle, Three & Four-Segment Instruction

Pipeline, Pipeline Conflicts and Solutions

6.4. Vector Processing, Applications, Vector Operations, Matrix Multiplication

Computer Arithmetic

7.1. Addition and Subtraction with Signed Magnitude Data, Addition and Subtraction with Signed 2’s Complement Data

7.2. Multiplication of Signed Magnitude Data, Booth Multiplication, Division of Signed magnitude Data, Divide Overflow

Input Output Organization

8.1. Input-Output Interface: I/O Bus and Interface Modules, I/O vs. Memory Bus, Isolated

vs. Memory-Mapped I/O

8.2. Asynchronous Data Transfer: Strobe, Handshaking

8.3. Modes of Transfer: Programmed I/O, Interrupt-Initiated I/O, Direct memory Access

8.4. Priority Interrupt: Polling, Daisy-Chaining, Parallel Priority Interrupt

8.5. Direct Memory Access, Input-Output Processor, DMA vs. IOP

Memory Organization

9.1 Memory Hierarchy, Main Memory, RAM and ROM Chips, Memory address Map,

Memory Connection to CPU, Auxiliary Memory (magnetic Disk, Magnetic Tape)

9.1 Associative Memory: Hardware Organization, Match Logic, Read Operation, Write

Operation

9.1 Cache Memory: Locality of Reference, Hit & Miss Ratio, Mapping, Write Policies

Laboratory Work

Student should be able to implement and simulate the algorithms by using high level

languages like C/Matlab and/or VHDL/Verilog. Laboratory work must include following

exercises:

1 Laboratory work for familiarizing with the syntax, data types, and operators of

Verilog/VHDL

2 Design of n-bit 2’s complement adder/subtractor

3 Design of Overflow detector in signed number addition

4 Design of parity generator and parity checker

5 Design of encoder and decoders

6 Design of multiplexer

7 Design of registers and memory

8 Memory Mapping

9 Design of control unit

10 Design of ALU

11 Design of CPU

12 Simulation of 5 stage or 4 stage or 3 stage pipelining

13 Simulation of addition and subtraction of signed 2’s complement data

14 Simulation of multiplication and division algorithms