Microprocessor and Computer Architecture - Syllabus

Embark on a profound academic exploration as you delve into the Microprocessor and Computer Architecture course () within the distinguished Tribhuvan university's BIT department. Aligned with the BIT Curriculum, this course (BIT151) seamlessly merges theoretical frameworks with practical sessions, ensuring a comprehensive understanding of the subject. Rigorous assessment based on a 60+20+20 marks system, coupled with a challenging passing threshold of , propels students to strive for excellence, fostering a deeper grasp of the course content.

This 3 credit-hour journey unfolds as a holistic learning experience, bridging theory and application. Beyond theoretical comprehension, students actively engage in practical sessions, acquiring valuable skills for real-world scenarios. Immerse yourself in this well-structured course, where each element, from the course description to interactive sessions, is meticulously crafted to shape a well-rounded and insightful academic experience.

Course Description:

This course aims at providing fundamental knowledge about computer architecture, instruction cycle, components of microprocessor, Intel 8085 and assembly programming.

Course Objectives:

The main objective of this course is to provide basic knowledge of components of microprocessor, block diagram and assembly language programming using Intel 8085, SAP1 and SAP2 computer architecture, timing diagrams, instruction cycles, machine cycles, control unit, central processing unit, RISC, CISC, Direct Memory Access, interrupts, serial and parallel interfaces

1.1 Definition of Microprocessor Components : Registers, ALU, Control and Timing, System Buses (Address, Data, Control), Microprocessor System with Bus Organization

1.2 SAP-1 Architecture: Block Diagram, and Function of each Block

      SAP-1 Instructions :LDA, ADD, SUB, OUT, HLT

       Fetch and Execution Cycle of SAP-1 Instructions with Timing

       Diagram

          • Fetch Cycle: Address State, Increment State, Memory State

          • Execution Cycle of LDA only