# Digital Logic - Unit Wise Questions

3. The term LOGIC GATES is to be transmitted as 12 bytes of data. Each character in the term has an ASCII value. The system uses odd parity and left most bit is used as parity bit. An additional parity byte is also sent after the term. The following bytes have arrived at their destination.

a. One of the bytes has an error after transmission. Locate which character contains an error.

b. Locate the bit that has been transmitted incorrectly.

c. Explain how you have arrived at your conclusion.

4. Convert (1011.110)_{2} into decimal and hexadecimal. (2.5+2.5)

4. Convert (51966.57)_{10} into octal and hexadecimal number system. (2.5+2.5)

5. Subtract (1011.11 - 1010.10) using 2's and 1's complement. (2.5+2.5)

5. Subtract (111000.110)_{2} - (110100.101)_{2} using both 2's and 1's complement.

9. a) Obtain the 9’s and 10’s complement of i) 13579 ii) 90090 decimal number.

b) Convert (6524275)_{8} = (?)_{16}

4. Show that the dual of the exclusive-OR is equal to its complement.

6. State and prove De-Morgan's Theorems.

6. Express the given function in sum of minterms.

F = y'z + wxy' + wzx' + w'x'z'

7. What are the special characteristics of IC digital logic family? Explain them in brief.

7. Simplify the Boolean function using don't care conditions d, in sum of products and product of sums form. (2.5+2.5)

F(A, B, C, D) = *π*(0,1,3,7,8,12) and *πd*(5,10,13,14)

8. A logic circuit implements the following Boolean function.

F=A’C+AC’D

It is found that the required input combination A=C=1 can never occur. Using K-map and proper don’t care condition find simpler expression for F and implement it using not gate only.

11. Given is a logic (switching) function F1 in the decimal list sum-of-minterms representation

1. Design the full adder circuit using 3 to 8 decoder and explain the working principle.

1. What is decoder? Design BCD to Decimal Decoder with truth table and logic diagram. (2+8)

1. Design a combinational circuit with four inputs and one output. The output is equal to 1 when (i) all the inputs are equal to 1 or (ii) none of the inputs are equal to 1 or (iii) an odd number of inputs are equal to 1.

2. Define combinational logic circuit. Design a combinational circuit whose input is a four-bit number and output is 2's complement of the input number. (2+8)

2. Implement the following function:

F = Σ(0,1,3,4,5,8,9,10,15) using

i) Decoder

ii) Multiplexer

iii) PLA

6. Design a decoder with three input lines but with only six output lines. If the value of the input corresponds to 6 or 7, then all output line should be asserted to signal an error.

7. Define Half-subtractor with truth table and logic diagram.

8. Implement a full subtractor with two half subtractor and one OR Gate.

8. What is decoder? Implement 8 x 1 MUX using 4 x 1 MUX. (1+4)

10. Design 8 to 1 Multiplexer using two 4 to 1 Multiplexers.

2. What is JK master slave flip-flop? Design its logic circuit, truth table and explain the working principle.

3. What do you mean by race condition in JK Flip Flop and mention the methods to overcome it? Explain Master Slave flip-flop using JK flip flop with logic circuit, truth table and timing diagram. (3+7)

9. Define SR latch with logic diagram and truth table. (1+4)

9. What is clocked RS flip-flop? Explain with logic diagram and characteristic table. (1+4)

12 Write short notes on:

a. PLA

b. Triggering of flip-flop.

12. Write short notes on: (2x2.5=5)

a) Parity generator

b) State diagram

3. What is ring counter? Explain ring counter with diagram, timing sequence and timing diagram. (2+8)

5. Explain with state diagram and excitation table for 3-bit binary counter.

10. Design Mod-3 synchronous counter.

10. Compare the logic of synchronous counter and ripple counter. (2+3)

11. Define shift register with its types.

11. Draw a parallel-In Parallel-Out Shift register and explain it.

12. Write short notes on : (2.5+2.5)

a) Binary parallel adder

b) Jonson counter