Digital System Design - Syllabus

Embark on a profound academic exploration as you delve into the Digital System Design course (DSD) within the distinguished Tribhuvan university's CSIT department. Aligned with the 2074 Syllabus, this course (CSC417) seamlessly merges theoretical frameworks with practical sessions, ensuring a comprehensive understanding of the subject. Rigorous assessment based on a 60+20+20 marks system, coupled with a challenging passing threshold of , propels students to strive for excellence, fostering a deeper grasp of the course content.

This 3 credit-hour journey unfolds as a holistic learning experience, bridging theory and application. Beyond theoretical comprehension, students actively engage in practical sessions, acquiring valuable skills for real-world scenarios. Immerse yourself in this well-structured course, where each element, from the course description to interactive sessions, is meticulously crafted to shape a well-rounded and insightful academic experience.

Course Description:

This course contains the introductory part of combinational Logic along with the clear concepts of K-Maps and Quine- Mc Cluskey Method. It also introduces sequential networks with flip flops and FSM. Another concept includes FPGA and VHDL and also testing and verification.

Course Objective:

The course objective is to provide ample knowledge on digital design process and to enhance the knowledge of hardware design in real scenarios.


Unit 1

Introduction of logic design, Digital System and Integration, Electronic Design Automation, IC Manufacturing, Logic Families, IC Design Techniques, IC characteristics: fan-out, power dissipation, propagation delay, and noise margin of TTL and CMOS integrated circuit logic devices

Unit 2

Review of Boolean Algebra and Combinational Logic, Canonical Form, Shannon's Expansion, Minterms, Maxterms, Prime Implication

unit 3

Combinational Network Design: K – Map, Synthesis and Minimization with K – Maps (AND – OR, OR-AND, NAND-NAND, NOR-NOR), Standard Combinational Networks

Unit 4

Quine- Mc Cluskey Method, Minimization of Boolean expression with Quine-Mc Cluskey method, PROMs and EPROMs, Programmable Array Logic (PAL), Programmed Logic Array (PLA), Gate Arrays, Programmable Gate Array, Full Custom Design

Unit 5

Sequential Networks: Transition from combinational to sequential network, Direct command flip flop, Initialization of sequential network, Level Enabled Flip-Flops, Synchronization of sequential networks, Edge-triggered Flip Flops, Synchronous and Asynchronous Signals

Unit 6

Sequential Networks as Finite State Machines: Standard Models, Realization with ASM Diagrams, Synthesis of Synchronous FSM, Time Behavior of Synchronous FSM, Design of input forming, Logic and Output Forming Logic of state machine.

Unit 7

Field Programmable Gate Arrays (FPGA), VHDL and its use in programmable logic devices (PLDs) like FPGA

Unit 8

Testing and Verification, Testing Logic Circuits, Combinational gate testing, Combinational network testing, Sequential Testing, Test vector generation, fault, fault model and fault detection, SA0, SA1, Design for Testability

Lab works

Laboratory Works:

Laboratory Exercise should cover the implementation of combinational and sequential circuits, FSM, FPGA and VHDL. Testing and verification of circuits.

Project Work:

Design a sample of tool kit by using the design concepts of the course.