Digital Logic Model Question

Group A

Attempt any two questions.     (2x10=20)

1. Design the full adder circuit using 3 to 8 decoder and explain the working principle.

2. What is JK master slave flip-flop? Design its logic circuit, truth table and explain the working principle.

3. The term LOGIC GATES is to be transmitted as 12 bytes of data. Each character in the term has an ASCII value. The system uses odd parity and left most bit is used as parity bit. An additional parity byte is also sent after the term. The following bytes have arrived at their destination.

a. One of the bytes has an error after transmission. Locate which character contains an error.

b. Locate the bit that has been transmitted incorrectly.

c. Explain how you have arrived at your conclusion.

Group B

Attempt any eight questions.     (8x5=40)

4. Show that the dual of the exclusive-OR is equal to its complement.

5. Explain with state diagram and excitation table for 3-bit binary counter.

6. Design a decoder with three input lines but with only six output lines. If the value of the input corresponds to 6 or 7, then all output line should be asserted to signal an error.

7. What are the special characteristics of IC digital logic family? Explain them in brief.

8. A logic circuit implements the following Boolean function.

    F=A’C+AC’D

It is found that the required input combination A=C=1 can never occur. Using K-map and proper don’t care condition find simpler expression for F and implement it using not gate only.

9. a) Obtain the 9’s and 10’s complement of i) 13579 ii) 90090 decimal number.

    b) Convert (6524275)₈ = (?)₁₆

10. Design 8 to 1 Multiplexer using two 4 to 1 Multiplexers.

11. Given is a logic (switching) function F1 in the decimal list sum-of-minterms representation

12 Write short notes on:

        a. PLA

        b. Triggering of flip-flop.