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Tribhuvan university CSIT 2065 Syllabus Computer Hardware Design

Computer Hardware Design - Syllabus

Course Overview and Structure
Syllabus Notes Old Questions Unit Wise Questions Question Bank

Embark on a profound academic exploration as you delve into the Computer Hardware Design course () within the distinguished Tribhuvan university's CSIT department. Aligned with the 2065 Syllabus, this course (CSC-312) seamlessly merges theoretical frameworks with practical sessions, ensuring a comprehensive understanding of the subject. Rigorous assessment based on a 80+20 marks system, coupled with a challenging passing threshold of , propels students to strive for excellence, fostering a deeper grasp of the course content.

This 3 credit-hour journey unfolds as a holistic learning experience, bridging theory and application. Beyond theoretical comprehension, students actively engage in practical sessions, acquiring valuable skills for real-world scenarios. Immerse yourself in this well-structured course, where each element, from the course description to interactive sessions, is meticulously crafted to shape a well-rounded and insightful academic experience.


Course Synopsis:  To introduce students to theoretical and practical concepts relevant to the structure and design of modern digital computers. The course covers computer architecture from gate-level logic through processor design to multiprocessor and network issues.
Goal: This course will make the student able to design the hardware components.

Units

Key Topics

  • Compiler Structure
    UN-1.1

    Analysis and Synthesis Model of Compilation, including different sub-phases within analysis and synthesis phases.

  • Compiler Concepts
    UN-1.2

    Basic concepts related to Compiler, including interpreter, simple One-Pass Compiler, preprocessor, macros, symbol table, and error handler.

  • Institutional Infrastructural Preparedness
    UN-1.3

    Institutional infrastructural preparedness refers to the readiness of government agencies and institutions to adopt and implement e-governance systems.

  • Human Infrastructural Preparedness
    UN-1.4

    Human infrastructural preparedness involves the development of skills and capacities of public officials and citizens to effectively use e-governance systems.

  • Technological Infrastructural Preparedness
    UN-1.5

    Technological infrastructural preparedness refers to the availability and quality of technology infrastructure, including computers, internet connectivity, and other digital tools.

  • Present Global Trends in E-Governance
    UN-1.6

    This topic analyzes the current state of E-Governance globally, including its growth, adoption, and impact on governments and societies.

  • Other Issues in E-Governance
    UN-1.7

    This topic covers additional topics and concerns related to E-Governance, including security, privacy, and ethics.

Gates, truth tables, and logic equations, Combinational logic and basic components. PLAs and ROMs, Memory elements. Finite state machines

Signed and unsigned numbers, Addition and subtraction. Design of ALUs.

Multiplication. Floating-point representation, Addressing: An application of unsigned integers: Byte-addressed memory, Byte ordering conventions, Big-endian, Little-endian, Pointers: Address vs. contents, Signed representations of integers

Design of the datapath of an ALU that executes the add, sub, and, or instructions, Control signals for the ALU, State elements and clocking,

Block view of a single-clock-cycle processor datapath, Control of the single-clock-cycle implementation, Control of the multiple-clock-cycle implementation, Exceptions and interrupts, Karnaugh maps, Multiplexors, Adders, Decoders, Data paths.  Single-cycle, control. Multi-cycle control, Microprocessor design: Microprogramming, Hardwired programming. Parallel processors, SIMD computers--Single Instruction Stream, Multiple Data Streams, MIMD Computers--Multiple Instruction Streams, Multiple Data, Streams; Programming MIMDs,  MIMDs connected by a single bus, MIMDs connected by a network, Future directions for parallel processors, Programming for parallel processors in a higher-level language

Outputs and next state as vectors of Boolean functions of inputs and present state,

Latches: Set and reset latches, SR latch, CSR latch, JK latch, D latch, Master-slave D flip-flop, Lightning introduction to finite state machines

A pipelined data path, Pipelined control, Visualization of pipelined data flow, Pipeline diagrams, Gantt charts, Data hazards, Compiler elimination of data hazards, Hardware control for data hazards: Reducing data hazards: Forwarding, Branch hazards, Performance of pipelined systems, Programming for a pipelined processor in a higher-level language

Hardware implementations of 1-bit memory, DRAM, SRAM, ROM, Hardware implementations of multiple-bit memory, DRAM, SRAM, ROM, SRAM and DRAM chip and system architectures, System bus architectures (processor to/from memory), Hierarchical memory systems, The processor-memory speed gap, Interleaved memory, Caches, Direct-mapped caches, Fully associative caches

Set-associative caches, Virtual memory, A common framework for memory hierarchies

Single-bus networks, Cache consistency, Networks and clusters.

Instructions, The fetch-execute cycle, Format of an assembly-language program, Comments, Directives, Data declarations in SPIM, Executable instructions, Survey of differences between SAL (Simple Abstract Language), human-coded MIPS assembly language, and true MIPS assembly language, Load-store architectures, Addressing modes, MIPS addressing modes and the corresponding formats in assembly language and object code, Implementation of I/O, Arrays, Usage of arithmetic and logical instructions in SAL, Branch instructions in SAL and SPIM, Stacks, Support for procedures in computer hardware, Alternatives to the MIPS approach