Digital Logic - Old Questions

2. Explain the 4 bit ripple counter and also draw a timing diagram.

A binary ripple counter consists of a series connection of complementing flip-flops (T or JK type), with the output of each flip-flop connected to the Clock Pulse input of the next higher-order flip-flop. The flip-flop holding the least significant bit receives the incoming count pulses. The diagram of a 4-bit binary ripple counter is shown in Fig. below. All J and K inputs are equal to 1. 

Fig: 4-bit ripple counter using JK Flip Flop

The small circle in the CP input indicates that the flip-flop complements during a negative-going transition or when the output to which it is connected goes from 1 to 0. The lowest-order bit Q₀ must be complemented with each count pulse. Every time Q₀ goes from 1 to 0, it complements Q₁. Every time Q₁ goes from 1 to 0, it complements Q₂, and so on.

State Sequence:

Timing Diagram:

In timing diagram Q₀ is changing as soon as the negative edge of clock pulse is encountered, Q1 is changing when negative edge of Q₀ is encountered(because Q₀ is like clock pulse for second flip flop) and so on.