Digital Logic 2065

In 16 X 1 multiplexer:

Input lines 16 = 2⁴ i.e. 4 Selection lines

Input lines will be I₍₀₎- I₍₁₅₎

Selection lines will be S₀ - S₃

Block Diagram

Truth Table

let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer.  We require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since, each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output.

The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data inputs of upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1 Multiplexer are I7 to I0. Therefore, each 8x1 Multiplexer produces an output based on the values of selection lines, s2, s1 & s0.

The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second stage. The other selection line, s3 is applied to 2x1 Multiplexer.

• If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is7 to I0 based on the values of selection lines s2, s1 & s0.
• If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I15 to I8 based on the values of selection lines s2, s1 & s0.

Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs as one 16x1 Multiplexer.

A binary ripple counter consists of a series connection of complementing flip-flops (T or JK type), with the output of each flip-flop connected to the Clock Pulse input of the next higher-order flip-flop. The flip-flop holding the least significant bit receives the incoming count pulses. The diagram of a 4-bit binary ripple counter is shown in Fig. below. All J and K inputs are equal to 1. 

Fig: 4-bit ripple counter using JK Flip Flop

The small circle in the CP input indicates that the flip-flop complements during a negative-going transition or when the output to which it is connected goes from 1 to 0. The lowest-order bit Q₀ must be complemented with each count pulse. Every time Q₀ goes from 1 to 0, it complements Q₁. Every time Q₁ goes from 1 to 0, it complements Q₂, and so on.

State Sequence:

Timing Diagram:

In timing diagram Q₀ is changing as soon as the negative edge of clock pulse is encountered, Q1 is changing when negative edge of Q₀ is encountered(because Q₀ is like clock pulse for second flip flop) and so on.

Full subtractor contains 3 inputs and 2 outputs (Difference and Borrow) as shown-

The truth table for full subtractor:

From the above truth table,

For the different functions in the truth table, the minterms can be written as 1,2,4,7, and similarly, for the borrow, the minterms can be written as 1,2,3,7. 

Since there are three inputs and a total of eight minterms. So we need 3-to-8 line decoder. The decoder generates the eight minterms for A, B & B_in.

Fig: Full subtractor with 3-to-8 Decoder and NOR gates

Input variables: A & B, Output variables: sumand carry

Logic diagram of half adder using NOR gates only:

Combinational circuit is a circuit which consist of logic gates whose outputs at any instant of time are determined directly from the present combination of inputs without regard to previous input. The combinational circuit do not use any memory.

• There will be combination of input variable for inputs.

• A combinational circuit can have number of inputs and number of outputs.

• For e.g. adders, subtractors, decoders, encoders etc.

  
  

Fig: Block diagram of combinational circuit