Digital Logic - Old Questions

1. Design the 4-bit synchronous up/down counter with timing diagram, logic diagram and truth table.

The counters which use clock signal to change their transition are called “Synchronous counters”. This means the synchronous counters depends on their clock input to change state values. In synchronous counters, all flip flops are connected to the same clock signal and all flip flops will trigger at the same time.

The  up and down counters can be implemented in a single counter called up/down counter. This can be selected from its input. The design of up/ down counter with JK flip flops is shown below.

The up/ down counter has “Up” and “Down” count modes by having 2 input AND gates, which are used to detect the appropriate bit conditions for counting operation. OR gates are used to combine the outputs of AND gate, from each JK flip flop.

We provide a up/ down control line which enables upper or lower series of AND gates to pass the outputs of JK flip flops, Q , Q’ to the next stage of flip flop, in the cascaded arrangement.

If the up /down control line is set to HIGH, then the top AND gates are in enable state and the circuit acts as UP counter. If the up /down control line is set to low, then the bottom AND gates are in enable state and the circuit acts as DOWN counter.