Digital Logic 2066
Long Questions:
Attempt any two questions: (2 × 10=20)
1. Design the 4-bit synchronous up/down counter with timing diagram, logic diagram and truth table.
The counters which use clock signal to change their transition are called “Synchronous counters”. This means the synchronous counters depends on their clock input to change state values. In synchronous counters, all flip flops are connected to the same clock signal and all flip flops will trigger at the same time.
The up and down counters can be implemented in a single counter called up/down counter. This can be selected from its input. The design of up/ down counter with JK flip flops is shown below.
The up/ down counter has “Up” and “Down” count modes by having 2 input AND gates, which are used to detect the appropriate bit conditions for counting operation. OR gates are used to combine the outputs of AND gate, from each JK flip flop.
We provide a up/ down control line which enables upper or lower series of AND gates to pass the outputs of JK flip flops, Q , Q’ to the next stage of flip flop, in the cascaded arrangement.
If the up /down control line is set to HIGH, then the top AND gates are in enable state and the circuit acts as UP counter. If the up /down control line is set to low, then the bottom AND gates are in enable state and the circuit acts as DOWN counter.
2. Design a full subtractor with truth table and logic gates.
3. Design a decimal adder with logical diagram and truth table.
Short Questions:
Attempt any eight questions: (8 × 5=40)
4. Differentiate between Analog and Digital system.
5. Convert the following octal numbers to hexadecimal.
a. 1760.46
b. 6055.263
6. Which gates can be used as inverts in additional to the NOT gate and how?
7. Draw a logic gates that implements the following
8. State and prove De-Morgan’s theorem 1st and 2nd with logic gates and truth table.
De-Morgans Theorem
De Morgan’s theorem is used to convert OR type of expression into AND type and vice-versa.It is further divided into two different types;
1st law:
It state that the total complement of sum is equal to the product of individual complement. i.e. (A+B)’=A’ ٠B’
Proof:
Input | Output | ||
A | B | (A+B)’ | A’ ٠B’ |
0 | 0 | 1 | 1 |
0 | 1 | 0 | 0 |
1 | 0 | 0 | 0 |
1 | 1 | 0 | |
2nd law:
It state that the total complement of the product is equal to the sum of individual complement. i.e. (A٠B)’ =A’+B’
Proof:
Input | Output | ||
A | B | (A٠B)’ | A’+B’ |
0 | 0 | 1 | 1 |
0 | 1 | 1 | 1 |
1 | 0 | 1 | 1 |
1 | 1 | 0 | 0 |
9. Reduce the following expressions using K-map 
10.Differentiate between a MUX and a DEMUX.
11. Explain the operation of Decoder.
12. What are the various types of shift registers?
13. What do you mean by Synchronous counter?