Digital Logic - Unit Wise Questions
1. What are the various types of numbering system use in the digital logic? Explain. Convert the 3EC816 into different numbering system that you know.
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4. Convert the following decimal numbers to the indicated bases.
(a) 7562.45 to octal
(b) 1938.257 to hexadecimal
(c) 175.175 to binary
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4. Perform the arithmetic operation (+42)+(-13) and (-42)-(-13) in binary using the signed -2's-complement representation for negative numbers.
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4. Convert the following hexadecimal number to decimal and octal numbers
(a) 0FFF (b) 3FFF
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4. Convert the following hexadecimal number to decimal and octal numbers.
a) 4FF
b) 6FED
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4. Convert the hexadecimal number 2BFC to binary and then to octal.
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4. What do you mean by the Gray code? What are its application?
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4. Differentiate between Analog and Digital system.
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5. Explain the error detection code with example.
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5. Convert the following decimal numbers into hexadecimal and octal number.
(a) 304 (b) 224
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5. Covert the following:
a) A08E. FA16 = (? )10
b) AE9. BOE16 = (? )2
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5. Convert the following decimal number into hexadecimal and octal.
a. 334
b. 225
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5. Convert the following decimal numbers into Hexadecimal and Octal numbers:
(a) 504
(b) 250
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5. Convert the following decimal numbers into hexadecimal and octal number.
(a) 220
(b) 1020
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5. Convert the following octal numbers to hexadecimal.
a. 1760.46
b. 6055.263
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10. Explain the Ripple Counter.
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5. Express the Boolean Function F = A + B' C in a sum of minterms .
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5. Proof the De-Morgan 1st and 2nd theorem with truth table and logic gates.
De-Morgans Theorem
De Morgan’s theorem is used to convert OR type of expression into AND type and vice-versa.It is further divided into two different types;
1st law:
It state that the total complement of sum is equal to the product of individual complement. i.e. (A+B)’=A’ ٠B’
Proof:
Input |
Output |
||
A |
B |
(A+B)’ |
A’ ٠B’ |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
|
2nd law:
It state that the total complement of the product is equal to the sum of individual complement. i.e. (A٠B)’ =A’+B’
Proof:
Input |
Output |
||
A |
B |
(A٠B)’ |
A’+B’ |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
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6. Explain the duality theorem with example.
It states that “Every algebraic expression deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are interchanged”. In a two-valued Boolean algebra, the identity elements and the elements of the set B are the same: 1 and 0. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's.
E.g. 
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6. State and prove commutative laws, associative laws and distributive law using logic gate and truth table.
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6. Proof the 1st and 2nd law of De Morgan’s theorems with logic gate and truth table.
De-Morgans Theorem
De Morgan’s theorem is used to convert OR type of expression into AND type and vice-versa.It is further divided into two different types;
1st law:
It state that the total complement of sum is equal to the product of individual complement. i.e. (A+B)’=A’ ٠B’
Proof:
Input | Output | ||
A | B | (A+B)’ | A’ ٠B’ |
0 | 0 | 1 | 1 |
0 | 1 | 0 | 0 |
1 | 0 | 0 | 0 |
1 | 1 | 0 | |
2nd law:
It state that the total complement of the product is equal to the sum of individual complement. i.e. (A٠B)’ =A’+B’
Proof:
Input | Output | ||
A | B | (A٠B)’ | A’+B’ |
0 | 0 | 1 | 1 |
0 | 1 | 1 | 1 |
1 | 0 | 1 | 1 |
1 | 1 | 0 | 0 |
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6. Which gates can be used as inverts in additional to the NOT gate and how?
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7. What do you mean by Universal gate? Realize the following logic gates using NOR gates.
(a) OR gate (b) AND gate
An universal gate is a gate which can implement any Boolean function without need to use any other gate type. The NAND and NOR gates are universal gates.
NOR gate as a Universal Gate
To prove that any Boolean function can be implemented using only NOR gates, we will show that the AND, OR, and NOT operations can be performed using only these
Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT functions.
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7. Show that both NAND gate and NOR gate are universal gates.
An universal gate is a gate which can implement any Boolean function without need to use any other gate type. The NAND and NOR gates are universal gates.
NAND gate
NAND gate is the combination of NOT gate and AND gate. If the two input values for an NAND gate are both 1, the output is 0; otherwise, the output is 1.
Fig: Various representations of a NAND gate
NAND gate as a Universal Gate
To prove that any Boolean function can be implemented using only NAND gates, we will show that the AND, OR, and NOT operations can be performed using only these gates.
Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT functions.
NOR gate
NOR gate is the combination of NOT gate and OR gate. If the two input values for NOR gate are both 0, the output value is 1; otherwise, the output is 0.
Fig: Various representations of a NOR gate
NOR gate as a Universal Gate
To prove that any Boolean function can be implemented using only NOR gates, we will show that the AND, OR, and NOT operations can be performed using only these
Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT functions.
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7. Draw a logic gates that implements the following
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8. State and prove De-Morgan’s theorem 1st and 2nd with logic gates and truth table.
De-Morgans Theorem
De Morgan’s theorem is used to convert OR type of expression into AND type and vice-versa.It is further divided into two different types;
1st law:
It state that the total complement of sum is equal to the product of individual complement. i.e. (A+B)’=A’ ٠B’
Proof:
Input | Output | ||
A | B | (A+B)’ | A’ ٠B’ |
0 | 0 | 1 | 1 |
0 | 1 | 0 | 0 |
1 | 0 | 0 | 0 |
1 | 1 | 0 | |
2nd law:
It state that the total complement of the product is equal to the sum of individual complement. i.e. (A٠B)’ =A’+B’
Proof:
Input | Output | ||
A | B | (A٠B)’ | A’+B’ |
0 | 0 | 1 | 1 |
0 | 1 | 1 | 1 |
1 | 0 | 1 | 1 |
1 | 1 | 0 | 0 |
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8. Prove that:
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12. Write short notes on (any two):
(a) State diagram
(b) De-Morgan's theorem
(c) TTL
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13. Write short notes on:-
a) CMOS
b) Universal gates
c) Error detection code
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5. Express the complement of the following function in sum of minterms.
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6. Reduce the following function using k-map
F = wxy + yz + xy'z + x'y
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6. Reduce the following function using k-map
F = B'D + A'BC' + AB'C + ABC'
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6. Simplify, the following Boolean function using three variable K-map.
a) F(X,Y,Z) = ∑(0,3,2,5)
b) F(A,B,C) = ∑(0,2,4,5,6)
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6. Describe the three Variable K-map with example.
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6. Explain the K-map with three variables.
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7. Simplify the Boolean expression.
prepare truth table to show that the simplified expression is correct or not?
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8. Write a procedure to reduce K-maps.
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9. Reduce the following expressions using K-map 
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9. Reduce the following expression using K-map.
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9. Simplify the Boolean function using K-Maps.
F = X’yz + X’yz’ +Xy’z’ +Xy’z
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2. What do you mean by full adder and full subtractor? Design a 3 to 8 line decoder using two 2 to 4 line decoder and explain it.
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2. Design a full subtractor with truth table and logic gates.
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3. Design the full subtractor circuit with using Decoder and explain the working principle.
Full subtractor contains 3 inputs and 2 outputs (Difference and Borrow) as shown-
The truth table for full subtractor:
From the above truth table,
For the different functions in the truth table, the minterms can be written as 1,2,4,7, and similarly, for the borrow, the minterms can be written as 1,2,3,7.
Since there are three inputs and a total of eight minterms. So we need 3-to-8 line decoder. The decoder generates the eight minterms for A, B & Bin.
Fig: Full subtractor with 3-to-8 Decoder and NOR gates
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3. Explain the full subtractor with using decoder.
Full subtractor contains 3 inputs and 2 outputs (Difference and Borrow) as shown-
The truth table for full subtractor:
From the above truth table,
For the different functions in the truth table, the minterms can be written as 1,2,4,7, and similarly, for the borrow, the minterms can be written as 1,2,3,7.
Since there are three inputs and a total of eight minterms. So we need 3-to-8 line decoder. The decoder generates the eight minterms for A, B & Bin.
Fig: Full subtractor with 3-to-8 Decoder and NOR gates
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4. Design a half subtractor circuit using only NAND gates.
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4. Design a half adder logic using only NOR gate.
Input
variables: A & B, Output variables: sum
and carry
Logic diagram of half adder using NOR gates only:
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4. Design a half adder logic using only NAND gates.
Soln:
Input
variables: A & B, Output variables: sumand carry
Logic diagram of half adder using NAND gates only:
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4. Design a half subtractor using only NOR gates.
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5. Design a half adder logic circuit using NOR gates only.
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7. Design half adder logic circuit using only universal gates.
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7. Explain the combination logic with examples.
Combinational circuit is a circuit which consist of logic gates whose outputs at any instant of time are determined directly from the present combination of inputs without regard to previous input. The combinational circuit do not use any memory.
There will be combination of input variable for inputs.
A combinational circuit can have number of inputs and number of outputs.
For e.g. adders, subtractors, decoders, encoders etc.
Fig: Block diagram of combinational circuit
Combinational logic circuit design procedure:
The problem is stated.
The number of available input variables and required output variables is determined.
The input and output variables are assigned letter symbols.
The truth table that defines the required relationships between inputs and outputs is derived.
The simplified Boolean function for each output is obtained.
The logic diagram is drawn.
Adders
Adders are the combinational circuits which is used to add two or more than two bits at a time.
Types of adders:
Half Adder
Full Adder
Half Adder:
A combinational circuit that performs the addition of bits is called half adder. This circuit needs two binary inputs and two binary outputs. The input variables designate the augend and addend bits; the output variables produce the sum and carry.
Fig: Block diagram
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8. What is combinational logic? What are its important features.
Combinational circuit is a circuit which consist of logic gates whose outputs at any instant of time are determined directly from the present combination of inputs without regard to previous input. The combinational circuit do not use any memory.
There will be combination of input variable for inputs.
A combinational circuit can have number of inputs and number of outputs.
For e.g. adders, subtractors, decoders, encoders etc.
Fig: Block diagram of combinational circuit
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11. Differentiate between combinational logic and sequential logic. List some applications of sequential logic.
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1. Implement the following function 
using
(a) Decoder
(b) Multiplexer
(c) PLA
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1. Implement the following function 
using
(a) Decoder
(b) Multiplexer
(c) PLA
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1. Draw a block diagram, truth table and logic circuit of a 16 x 1 multiplexer and explain its working principle.
In 16 X 1 multiplexer:
Input lines 16 = 24 i.e. 4 Selection lines
Input lines will be I(0)- I(15)
Selection lines will be S0 - S3
Block Diagram
Truth Table
let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer. We require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since, each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output.
The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data inputs of upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1 Multiplexer are I7 to I0. Therefore, each 8x1 Multiplexer produces an output based on the values of selection lines, s2, s1 & s0.
The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second stage. The other selection line, s3 is applied to 2x1 Multiplexer.
- If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is7 to I0 based on the values of selection lines s2, s1 & s0.
- If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I15 to I8 based on the values of selection lines s2, s1 & s0.
Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs as one 16x1 Multiplexer.
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1. What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it.
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1. Draw a block diagram, truth table and logic circuit of 1x16 Demultiplexer and explain its working principle.
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2. Differentiate between PAL and PLA. Design a counter as shown in the state diagram below
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1. What is decoder? Implement the following using decoder.
(a) F (W X Y Z) = Σ (0,1,3,4,8,9,10)
(b) F (W X Y Z) = Σ (1,3,5,6,11,13,14)
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1. Explain the magnitude comparator and also design a logic diagram for 4 bit magnitude comparator.
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1. Design Magnitude comparator and also design a logic diagram for a 4 bit magnitude comparator.
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3. Draw a block diagram, truth table and logic circuit of 1*16 Demultiplexer and explain its working principle.
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2. What do you mean by decoder? Design a 3 to 8 line decoder using 2 to 4 line decoder and explain it.
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2. Design a magnitude comparator using logic gates and truth table.
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3. The following is a truth table of a 3-input,4 output combinational circuit. Tabulate the PAL programming table for the circuit and mark for the circuit and mark the fuses to be blown in a PAL diagram.
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3. What is magnitude comparator? Design a logic circuit for 4 bit comparator and explain it.
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3. What is demultiplexer? Draw its block diagram and explain its working principle.
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3. Design a decimal adder with logical diagram and truth table.
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7. Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less than the input.
Truth Table that defines the required relationship between inputs and outputs:
Map for output A:
Map for output B:
Map for output C:
Now, Drawing Logic Diagram for A, B & C:
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7. Design a combinational circuit with three inputs and six outputs. The output binary number should be the square of the input binary number.
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6. Design an encoder using universal gates.
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8. Implement half adder using 2-4 decoder.
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6. Design a multiplexer 4x1 using only universal gates.
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9. Design and explain the Decimal adder with truth table and suitable diagram.
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9. Design the priority encoder circuit.
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7. Design the Decoder using Universal gates.
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8. Differentiate between Multiplexer and demultiplexer.
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8. Draw a logic circuit of 8*1 multiplexer.
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8. Explain the PLA (Programmable Logic Array).
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8. Draw a logic circuit of 4 x 1 multiplexer.
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9. Design the 4 bit parallel binary adder.
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10.Differentiate between a MUX and a DEMUX.
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10. Explain the PLA with the block diagram.
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11. Design the decimal adder.
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11. Draw a 3 to 8 decoder circuit and explain its operation.
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11. Explain the operation of Decoder.
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11. Explain the decoder and design with universal gates.
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12. Design a 4 input multiplexer using logic diagram and truth table.
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12. Explain the decimal adder.
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12. Explain the programmable logic array.
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13. Write short notes on (any two):
a. Decoder b. Integrated circuit c. PLA.
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13. Write short notes on :
(a) Programmable Logic Array
(b) Triggering at flip-flop
(c) Memory Unit
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1. Design and implement with logic diagram of synchronous 3 bit up down counter using J-K flip flop.
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1. Design the 4-bit synchronous up/down counter with timing diagram, logic diagram and truth table.
The counters which use clock signal to change their transition are called “Synchronous counters”. This means the synchronous counters depends on their clock input to change state values. In synchronous counters, all flip flops are connected to the same clock signal and all flip flops will trigger at the same time.
The up and down counters can be implemented in a single counter called up/down counter. This can be selected from its input. The design of up/ down counter with JK flip flops is shown below.
The up/ down counter has “Up” and “Down” count modes by having 2 input AND gates, which are used to detect the appropriate bit conditions for counting operation. OR gates are used to combine the outputs of AND gate, from each JK flip flop.
We provide a up/ down control line which enables upper or lower series of AND gates to pass the outputs of JK flip flops, Q , Q’ to the next stage of flip flop, in the cascaded arrangement.
If the up /down control line is set to HIGH, then the top AND gates are in enable state and the circuit acts as UP counter. If the up /down control line is set to low, then the bottom AND gates are in enable state and the circuit acts as DOWN counter.
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2. Design clocked sequential circuit of the following state diagram by using JK flip-flop.
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3. What is JK master slave flip-flop? Design its logic circuit, truth table and explain the working principle.
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3. Explain the Master-slave S-R flip-flop with logic diagram, truth table and timing diagram.
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3. Design a master-slave S-R flip flop with logic diagram and truth table.
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8. Design a 5 x 32 decoder with four 3 x 8 decoder with enable and one 2 x 4 decoder. Use block diagrams only.
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7. What is J-K flip flop? Explain.
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7. What do you mean by D-flip-flop?
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8. What is sequential logic? What are the important features?
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11. Explain master slave J-K flipflop.
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9. How JK flip flop can convert into a D-flip flop?
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9. Describe the clocked RS flip-flop.
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9. What is flip-flop? Mention the application of flip-flop.
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10. How does a J-K flip flop differs from an S-R flip flop in its basic operations? Explain.
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10. What do you mean by triggering of flip flop?
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11. Explain the R-S flip flop with truth table.
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12. What do you mean by clocked RS flip-flop ?Explain
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13. What do you mean by Synchronous counter?
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13. Write short note on (any two):
a) Flip flop
b) Synchronous Counter
c) Digital systems.
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13. Write short notes on :
(a) Asynchronous counter
(b) Multiplexers
(c) State reduction table
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2. Design the mod-6 asynchronous counter and explain with truth table.
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2. Explain the 4 bit ripple counter and also draw a timing diagram.
A binary ripple counter consists of a series connection of complementing flip-flops (T or JK type), with
the output of each flip-flop connected to the Clock Pulse input of the next higher-order flip-flop. The flip-flop
holding the least significant bit receives the incoming count pulses. The diagram of a 4-bit binary ripple
counter is shown in Fig. below. All J and K inputs are equal to 1.
Fig: 4-bit ripple counter using JK Flip Flop
The small circle in the CP input indicates that the flip-flop complements during a negative-going transition or when the output to which it is connected goes from 1 to 0. The lowest-order bit Q0 must be complemented with each count pulse. Every time Q0 goes from 1 to 0, it complements Q1. Every time Q1 goes from 1 to 0, it complements Q2, and so on.
State Sequence:
Timing Diagram:
In timing diagram Q0 is changing as soon as the negative edge of clock pulse is encountered, Q1 is changing when negative edge of Q0 is encountered(because Q0 is like clock pulse for second flip flop) and so on.
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2. Design a 3 bit synchronous counter and explain it.
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2. What do you mean by asynchronous counter? Design a mod-6 synchronous counter using T flip-
flops.
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2. What do you mean by ripple counters? Explain with timing diagram.
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3. What do you mean by ripple counter? Explain the design procedure of sequential circuits.
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10. What is the difference between a serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial. What type of register is needed?
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10. Explain shift register with parallel load. Highlight on its practical implications.
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9. Mention the difference types of shift register.
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11. Design a 4-bit binary ripple counter with D flip-flops.
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9. What are the various types of shift registers?
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12. Write short notes on (any two):
(a) SIMM
(b) RTL
(c) Parity Checker
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10. Draw a parallel-parallel-out shift register and explain it.
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10. Draw a logic diagram of a 4 bit ripple counter using D-flip flop.
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10. What do you mean by synchronous counter? Explain with truth table.
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10.What do you mean by Ripple counters?
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11. What are the shift Register operations?
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11. Differentiate between a counter a shift register.
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11. Explain the 4 bit ripple counter.
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12. Describe the Ripple counter.
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12. Mention the difference types of shift register and explain.
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12. What are the various types of shift registers?
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12. What do you mean by shift registers? Explain.
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12. Explain the shift register with example.
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13. Write short notes on:
(a) Registers. (b) Digital. (c) EBCDIC.
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13. Explain the serial-In, parallel out shift register.
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13. Write short note on (any two):
a) Binary counter
b) State reduction
c) Negative edge triggering
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